The method and system relate to assuring that data stored in a large shared L2 cache memory in a multi-processor environment and the data of the main memory are either identical or are controlled so that stale and current data are not confused with each other.
In a shared memory multiprocessor of the prior art, with a separate L1 cache memory for each processor (hereinafter referred to as an L1 cache), it is possible to have many copies of any one instruction operand: one copy in the main memory and one copy in each individual L1 cache memory. When one copy of an operand is changed, the other copies of the operand must be changed also, i.e., to provide cache coherence. Cache coherence is the discipline that ensures that changes in the values of shared operands are propagated throughout the system in a timely fashion.
There are three distinct levels of system behavior to be considered with respect to cache coherence:
In level 1, every write operation appears to occur instantaneously.
In level 2, all processes see exactly the same sequence of changes of values for each separate operand.
In level 3, different processes may see an operand assume different sequences of values. (This is considered noncoherent behavior.)
In both level 2 behavior (where all processes see exactly the same sequence of changes of values for each separate operand) and in level 3 behavior (where different processes may see an operand assume different sequences of values, e.g., non coherent behavior), a program can observe stale data.
In a large shared-memory multiprocessor, providing a system level cache memory (hereinafter referred to as an L2 cache) of the recently accessed contents of memory, along with an efficient means to handle system-wide cache coherency, can theoretically be accomplished with a single system cache directory away by requiring the contents of the respective processor level L1 cache memories to be a subset of the L2 system cache memory. Unfortunately, when the combined size of the processor L1 cache memories is sufficiently large, there is the problem that an inclusive L2 system cache approach can become impractical because the resulting size of the L2 system cache memory required to work effectively becomes too big.
While one possible solution to the above problem is to maintain a single system directory only partially backed by cache data, this proves difficult in practice. This is because the logic must now evaluate which entries have data and which do not when determining a system cache data hit.